Summary
1s complement
- add 1 to the result if there’s a carry out on MSB
2s complement
- ignore the carry out on MSB
Concept
Overflow
- result of operation exceeds the range of the signed number
- occurs when the carry in and carry out of the MSB is different
- eg.
- +ve + +ve -> -ve, or
- -ve + -ve -> +ve
Application
1s complement(4-bit)
2s complement(4-bit)
1s complement zero addition
add 1 if there’s a carry out on MSB because there are two 0s