data hazards

Summary

RAW dependency

• when a subsequent instruction reads from the destination register, written to by a previous instruction
• if read before written -> stale result, not the latest value

# looking at $2
sub $2, $1, $3    #1
and $12, $2, $5   #2
or $13, $6, $2    #3
add $14, $2, $2   #4
sw  $15, 100($2)  #5 

• solution: stalling

• solution: forwarding - forward the result from pipeline register, instead of waiting for WB

recall that MEM/WB also stores the ALU result, and take forwarded data from the previous cycle only

Load word

• requires memory access
• value is only available after MEM

lw $2,  20($3)
and $12, $2, $5
or $13, $6, $2
add $14, $2, $2 
sw  $15, 100($2) 

Concept

Data hazards

• data dependencies between instructions
• RAW - read after write
  • most important
  • can cause delay
• WAR - write after read
  • inconsequential in MIPS
• WAW - write after write
  • inconsequential in MIPS

Forwarding

• forward the result to any subsequent instruction before WB
• can come from EX/MEM or MEM/WB registers(for lw only from MEM/WB)
• go to the subsequent instruction’s EX stage

Application

Pipeline from MIPS code

lw $2, 0($1)    #1
lw $1, 100($6)  #2
sub $6, $1, $2  #3
add $6, $2, $6  #4
and $3, $6, $0  #5
sw $6, 50($1)   #6

• without forwarding

• with forwarding

• alternate forwarding

there is no more “correct” method, although the first one is more aligned with the examples in the slide